DS90LVTMTC: DS90LV – V or 5V LVDS Driver/Receiver, Package: Soic Narrow, Pin Nb= DS 90 LV TMTC · DS90LVTMTCX: DS90LV to +85°C SOIC M-LVDS, full duplex, type 1. DS90LVTM/TMTC. 1. 1. LVDS. or 5. to +85°C SOIC, TSSOP DS92LVATM. 1. SOIC M-LVDS, full duplex, type 2. DS91DTM. 1. 1. M-LVDS. MHz. . to +85°C. SOIC M-LVDS, full duplex, type 1. DS90LVTM/TMTC. 1.

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M-LVDS is optimized for multipoint including features critical to multipoint applications such as: Total maximum jitter 31 ps 1. Serializes 24 bits at 5 to 43 MHz to Mbps?

The diagram helps you to quickly? SDV serializers, cable drivers, equalizers, reclockers, etc. National has recently moved to 2-letter package code suf? Fractional-N PLL programmable up to 4th order? Choice of second reclocked output or low-jitter, differential, data-rate clock output?


Industrial Connectivity Made Easy. Single and dual channel integrated 2: Low 34 mA typ power consumption? A complete evaluation kit reference design is available.

Channel Link SerDes n: Drives 10m twisted pair cable?

This evaluation kit can be reworked to accept non MHz, nonbit devices if necessary. National leverages its high performance analog signal conditioning expertise to provide solutions that extend cable reach, reduce jitter and transmit ultra-clean video signals that meet or exceed speci?

This reduces the amplitude difference between the ds09lv048a frequency and the higher frequency components of the bit stream. Signal conditioners pre-emphasis, equalization, etc.

C industrial temperature range. Splitters and crosspoints create multiple copies of your clock or can be used for clock redundancy.

DS90LVATMTCX Datasheet(PDF) – TI store

Zero volts on the receiver thresholds will always result in a logic LOW. In addition to providing a failsafe, type 2 receivers can be used in Wired-Or logic. Up to 10 dB improvement over next best monolithic competitor?


The DS90UR deserializer requires no external tmttc reference, reducing receiver board complexity and cost. Very low power down current? Two differential, reclocked outputs? Pre-emphasis or de-emphasis pre-distorts the output signal to compensate for the?

Partially integrated adjustable loop? DP reference design available DP reference design available interface. Common mode extended to F Coaxial Cable 4. Integrated termination saves board area, improves signal quality?


DC-balance encoding for AC-coupled and optical interconnects? Available with type 1 and type 2 failsafe receiver thresholds The M-LVDS standard includes 2 types of receiver thresholds.

Ds90lv048w other brand or product names are trademarks or registered trademarks of their respective holders. Receiver automatically locks to any data pattern without external clock?